Designing HPC silicon
at the frontier.

Architecture

Architecture Team

Decide where every watt goes.

Architecture defines what "good" means — and proves it before a line of RTL is written. This team owns the chip's micro-architecture, the performance models that back every decision, and the trade-offs that pick where to spend area and power. We hire people who see the whole system and can quantify it.

• Micro-architecture across compute, memory hierarchy, and interconnect
• Performance modeling: cycle-accurate, analytical, and post-silicon correlation
• Design-space exploration and PPA trade-off studies
• Power architecture: budgets, voltage/clock domains, and the thermal envelope
• Workload characterisation that turns real AI models into design targets

Typical positions

• Performance Architect
• Micro-architecture Engineer
• Performance Modeling Engineer
• Power Architect
• Architecture Manager / Director

All levels: individual contributors and management.

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Design front-end

Frontend Implementation Team

Architecture into silicon-ready logic.

This team turns micro-architecture into synthesisable, verifiable, high-performance RTL — and the verification that earns first-pass silicon. We hire engineers who own a block from spec to clean, proven logic and refuse to ship anything they can't stand behind.

• Production SystemVerilog/Verilog for compute, memory, and interconnect blocks
• UVM testbenches, coverage closure, and formal / assertion-based verification
• Block- to chip-level design and verification sign-off
• FPGA / emulation bring-up for full-system pre-silicon validation
• PPA-driven micro-architecture and RTL trade-offs

Typical positions

• RTL Design Engineer
• Design Verification Engineer
• Emulation / FPGA Engineer
• Design / DV Manager / Director

All levels: individual contributors and management.

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Design back-end

Backend Implementation Team

Where the design meets physics.

This team takes RTL to a manufacturable, timing-clean layout on advanced nodes — plus the test infrastructure that proves every die. Back-end implementation is where PPA is finally won or lost. We hire engineers who close timing under aggressive targets and sign off with confidence.

• Synthesis, floorplanning, place & route, and clock-tree synthesis
• Timing closure and STA sign-off across PVT corners
• Power, IR, EM, and physical verification (DRC / LVS)
• Design-for-test: scan, MBIST, ATPG, and coverage closure
• Block- and chip-level PPA ownership

Typical positions

• Physical Design Engineer
• STA / Timing Engineer
• DFT Engineer
• Physical Design Manager / Director

All levels: individual contributors and management.

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IP & interfaces

IP Team

Move data on and off the chip.

The IP team owns the high-speed interfaces that set the chip's real-world bandwidth and latency — memory and I/O subsystems integrated from architecture through post-silicon. We hire engineers who live at the boundary where the chip meets the rest of the system.

• DDR / LPDDR / HBM memory controller architecture and PHY integration
• High-speed SerDes: link training, equalisation, and signal integrity
• PCIe Gen4/5/6 and CXL host interface
• QoS, scheduling, and end-to-end bandwidth / latency targets
• Bring-up, training, and post-silicon characterisation across PVT

Typical positions

• Memory Controller Engineer
• SerDes Engineer
• PCIe / CXL Engineer
• IP Manager / Director

All levels: individual contributors and management.

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AI-native infrastructure

Agentic AI Team

Build the AI-native foundation.

We are not "an IC company that adopted AI" — we are a company grown, from day one, on agentic-AI infrastructure. This small, elite team doesn't build the chip itself; it builds the systems, workflows, and culture that make everyone building the chip move faster. Few people, each able to take on ten — and see the whole map.

• Core agent infrastructure — orchestration, tool interfaces, permissioning, audit — turning LLMs from "chat" into reliable executors inside real systems
• Agent-driven company workflow, so adding a process means "define a goal + give agents the right tools and limits"
• Bringing AI into the IC design flow: RTL generation/refactor, verification, design-space exploration, cross-EDA orchestration
• Defining the human–agent–tool collaboration model and an "agent-by-default, humans for the judgement calls" culture

Typical positions

• Agent Infrastructure Engineer
• AI Systems / LLM Engineer
• Workflow Automation Engineer
• EDA Flow Integrator
• Agentic AI Lead

All levels: individual contributors and management.

Honest note: we're not 100% agentic yet — that's exactly why we're hiring. If you want a blank page to define yourself, this is it.

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Infrastructure & CAD

IT CAD Team

The ground the company runs on.

This team builds the foundation everyone else stands on — from the EDA/CAD flows and CI that make the hardware org fast, to the servers, network, and security that keep the whole company productive. We hire engineers who treat infrastructure as a product, not an afterthought.

• EDA / CAD flow automation: synthesis, P&R, STA, and verification flows end-to-end
• CI and regression infrastructure for RTL, DV, and physical design
• Internal tooling, CLIs, and dashboards for chip engineers
• Servers, network, storage, and backups across on-prem and cloud
• Endpoint and identity: provisioning, MDM, SSO, access control, and audit

Typical positions

• CAD / EDA Flow Engineer
• CI / DevOps Engineer
• IT Systems & Network Engineer
• IT / CAD Manager

All levels: individual contributors and management.

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